In a prior art disk array controller architecture, one internal bus is used or two buses, that is, a control bus by a built-in MPU and a user data transfer bus between a host interface and a disk device interface are used.
Further, as disclosed in JP-A-6-180623, a dedicated circuit such as a FIFO (First-in First-out) for speed control is needed between the host interface and the disk device. In the prior art, in order to fully derive the transfer performance of the host interface and the drive without causing a performance neck by an internal bus of the array controller, it is necessary to increase the transfer rate of the internal bus to a sufficiently high rate as compared with the transfer rate of the host interface and the drive interface, and a dedicated circuit such as FIFO are required between the high speed internal bus and the host interface and the drive interface, and in a disk array controller having a plurality of channels of host interface and disk device interface, this is a factor of high cost of the disk array controller and the disk array system.